Επείγουσα Ερώτηση

[zorro_now]

Γεια σας εκεί!

Είμαι προσπαθεί να γράψει ένα verilog κώδικα για το αρχείο και το αρχείο και ένα κλίνης αλλά
εκτελέστε την προσομοίωση μου δίνει λάθος στο πάγκο δοκιμής:
Lv RA, RB, RW, WriteEnable και BusW δεν μπορεί να anet.

θα μπορούσε οποιαδήποτε να με βοηθήσει;

αυτός είναι ο κωδικός

ενότητα reg_file (CLK, RST, RA, RB, RW, WriteEnable, BusW, BusA, BusB)?
εισροών CLK, RST?
εισροών [4:0] RA, RB, RW?
εισροών WriteEnable?
εισροών [31:0] BusW?
εξόδου [31:0] BusA, BusB?
wire [31:0] x, Z?

/ / αποκωδικοποιητή για να i / p για το μητρώο
αντιστοιχίσετε
Z [0] = (~ RW [4] & ~ RW [3] & ~ RW [2] & ~ RW [1] & ~ RW [0]),
Z [1] = (~ RW [4] & ~ RW [3] & ~ RW [2] & ~ RW [1] & RW [0]),
Z [2] = (~ RW [4] & ~ RW [3] & ~ RW [2] & RW [1] & ~ RW [0]),
Z [3] = (~ RW [4] & ~ RW [3] & ~ RW [2] & RW [1] & RW [0]),
Z [4] = (~ RW [4] & ~ RW [3] & RW [2] & ~ RW [1] & ~ RW [0]),
Z [5] = (~ RW [4] & ~ RW [3] & RW [2] & ~ RW [1] & RW [0]),
Z [6] = (~ RW [4] & ~ RW [3] & RW [2] & RW [1] & ~ RW [0]),
Z [7] = (~ RW [4] & ~ RW [3] & RW [2] & RW [1] & RW [0]),
Z [8] = (~ RW [4] & RW [3] & ~ RW [2] & ~ RW [1] & ~ RW [0]),
Z [9] = (~ RW [4] & RW [3] & ~ RW [2] & ~ RW [1] & RW [0]),
Z [10] = (~ RW [4] & RW [3] & ~ RW [2] & RW [1] & ~ RW [0]),
Z [11] = (~ RW [4] & RW [3] & ~ RW [2] & RW [1] & RW [0]),
Z [12] = (~ RW [4] & RW [3] & RW [2] & ~ RW [1] & ~ RW [0]),
Z [13] = (~ RW [4] & RW [3] & RW [2] & ~ RW [1] & RW [0]),
Z [14] = (~ RW [4] & RW [3] & RW [2] & RW [1] & ~ RW [0]),
Z [15] = (~ RW [4] & RW [3] & RW [2] & RW [1] & RW [0]),
Z [16] = (RW [4] & ~ RW [3] & ~ RW [2] & ~ RW [1] & ~ RW [0]),
Z [17] = (RW [4] & ~ RW [3] & ~ RW [2] & ~ RW [1] & RW [0]),
Z [18] = (RW [4] & ~ RW [3] & ~ RW [2] & RW [1] & ~ RW [0]),
Z [19] = (RW [4] & ~ RW [3] & ~ RW [2] & RW [1] & RW [0]),
Z [20] = (RW [4] & ~ RW [3] & RW [2] & ~ RW [1] & ~ RW [0]),
Z [21] = (RW [4] & ~ RW [3] & RW [2] & ~ RW [1] & RW [0]),
Z [22] = (RW [4] & ~ RW [3] & RW [2] & RW [1] & ~ RW [0]),
Z [23] = (RW [4] & ~ RW [3] & RW [2] & RW [1] & RW [0]),
Z [24] = (RW [4] & RW [3] & ~ RW [2] & ~ RW [1] & ~ RW [0]),
Z [25] = (RW [4] & RW [3] & ~ RW [2] & ~ RW [1] & RW [0]),
Z [26] = (RW [4] & RW [3] & ~ RW [2] & RW [1] & ~ RW [0]),
Z [27] = (RW [4] & RW [3] & ~ RW [2] & RW [1] & RW [0]),
Z [28] = (RW [4] & RW [3] & RW [2] & ~ RW [1] & ~ RW [0]),
Z [29] = (RW [4] & RW [3] & RW [2] & ~ RW [1] & RW [0]),
Z [30] = (RW [4] & RW [3] & RW [2] & RW [1] & ~ RW [0]),
Z [31] = (RW [4] & RW [3] & RW [2] & RW [1] & RW [0])?

αντιστοιχίσετε x = WriteEnable & Z?

πάντα @ (posedge CLK)
αρχίζω
εάν (ΤΥ)
y = 0?
else if (x)
y = BusW?
τέλος
MUX MUX1 (y, BusA, RA)?
MUX MUX2 (y, BusB, RB)?

endmodule

/ * Εγγραφή
ενότητα beh_register (CLK, RST, y, x, BusW)?
εισροών CLK, RST?
εισροών [31:0] x, BusW?
εξόδου [31:0] y?
reg [31:0] y?
πάντα @ (posedge CLK)
αρχίζω
εάν (ΤΥ)
y = 0?
else if (x)
y = BusW?
τέλος
endmodule * /

/ / MUX
ενότητα MUX (INP, OUT, επιλέξτε)?
εισροών [31:0] INP?
εισροών [4:0] επιλέξετε?
εξόδου Out?
reg Out?
@ πάντα (ή επιλέξτε INP)
περίπτωση (επιλέξτε)
5'b00000: Out INP = [0]?
5'b00001: Out = INP [1]?
5'b00010: Out INP = [2]?
5'b00011: Out = INP [3]?
5'b00100: Out = INP [4]?
5'b00101: Out = INP [5]?
5'b00110: Out = INP [6]?
5'b00111: Out = INP [7]?
5'b01000: Out = INP [8]?
5'b01001: Out = INP [9]?
5'b01010: Out = INP [10]?
5'b01011: Out = INP [11]?
5'b01100: Out = INP [12]?
5'b01101: Out = INP [13]?
5'b01110: Out = INP [14]?
5'b01111: Out = INP [15]?
5'b10000: Out = INP [16]?
5'b10001: Out = INP [17]?
5'b10010: Out = INP [18]?
5'b10011: Out = INP [19]?
5'b10100: Out = INP [20]?
5'b10101: Out = INP [21]?
5'b10110: Out = INP [22]?
5'b10111: Out = INP [23]?
5'b11000: Out = INP [24]?
5'b11001: Out = INP [25]?
5'b11010: Out = INP [26]?
5'b11011: Out = INP [27]?
5'b11100: Out = INP [28]?
5'b11101: Out = INP [29]?
5'b11110: Out = INP [30]?
5'b11111: Out = INP [31]?
endcase
endmodule

reg_testbench ενότητα?

reg [31:0] BusA, BusB?
σύρμα CLK, RST?
wire [4:0] RA, RB, RW?
σύρμα WriteEnable?
wire [31:0] BusW?

reg_file stmcrct (CLK, RST, RA, RB, RW, WriteEnable, BusW, BusA, BusB)?
αρχική
αρχίζω

BusW = 32'b00000000000000000000111111111111?
WriteEnable = 1'b1?
RW = 5'b00000?
# 10
BusW = 32'b00011000000111000000111111111111?
WriteEnable = 1'b1?
RW = 5'b00001?
# 10
WriteEnable = 1'b0?
RA = 5'b00000?
RB = 5'b00001?
τέλος
αρχική
$ παρακολουθεί ( "BusW =% b \ nBusA =% b \ nBusB =% b \ n", BusW, BusA, BusB)?
endmodule

 

[dcreddy1980]

Σε testbench σας, όταν έχετε λιμένα χαρτογραφήθηκαν τον σχεδιασμό, και έχει δηλώσει:

reg [31:0] BusA, BusB?
σύρμα CLK, RST?
wire [4:0] RA, RB, RW?
σύρμα WriteEnable?
wire [31:0] BusW?

Αλλαγή στη διεύθυνση:

wire [31:0] BusA, BusB?
reg CLK, RST?
reg [4:0] RA, RB, RW?
reg WriteEnable?
reg [31:0] BusW?